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ISL45042A
Data Sheet August 29, 2007 FN6158.3
LCD Module Calibrator
The VCOM voltage of an LCD panel needs to be adjusted to remove flicker. The ISL45042A can be used to digitally adjust a panel's VCOM voltage by controlling its output sink current. The output of the ISL45042A is connected to an external voltage divider and an external VCOM buffer amplifier. In this application, the user can control the VCOM voltage with 7-Bit accuracy (128 steps). Once the desired VCOM setting is obtained, the settings can be stored in the non-volatile EEPROM memory, which would then be automatically recalled during every power-up. The VCOM adjustment and non-volatile memory programming is through a single interface pin (CTL). Once the desired programmed value is obtained the Counter Enable pin (CE) can be used to prevent further adjustment or programming. The full-scale sink current of the ISL45042A is set using an external resistor connected to the SET pin. The full-scale sink current determines the lowest voltage of the external voltage divider. The ISL45042A is available in an 8 Ld 3mmx3mm TDFN package with a maximum thickness of 0.8mm for ultra thin LCD panel design.
Features
* 128-Step Adjustable Sink Current Output * 2.6V to 3.6V Logic Supply Voltage Operating Range * 4.5V to 20V Analog Supply Voltage Range * Rewritable EEPROM for storing the optimum VCOM value * Output Adjustment Enable/Disable Control * Output Guaranteed Monotonic Over-Temperature * Two Pin Adjustment, Programming and Enable * Ultra Thin 8 Ld 3mmx3mm DFN (0.8mm max) * Pb-free available (RoHS compliant)
Applications
* LCD Panels
Ordering Information
PART NUMBER (Note) ISL45042AIRZ ISL45042AIRZ-T* TEMP. RANGE PART (C) MARKING 42AZ 42AZ PACKAGE (Pb-Free) PKG. DWG. # L8.3x3A L8.3x3A
-40 to +85 8 Ld 3x3 TDFN -40 to +85 8 Ld 3x3 TDFN Tape and Reel -40 to +85 8 Ld 3x3 TDFN Tape and Reel
Pinout
ISL45042A (8 LD TDFN) TOP VIEW
OUT 1 AVDD 2 N/C 3 GND 4 8 7 6 5 SET CE CTL VDD
ISL45042AIRZ-TK* 42AZ
L8.3x3A
*Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2005, 2006, 2007. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
ISL45042A Pin Descriptions
PIN OUT FUNCTION Adjustable Sink Current Output Pin. The current sinks into the OUT pin is equal to the DAC setting times the maximum adjustable sink current divided by 128. See SET pin function description for the maxim adjustable sink current setting. High-Voltage Analog Supply. Connects to top of external resistor divider to determine the VCOM voltage. Typically 10V to 20V. Bypass to GND with 0.1F de-coupling capacitor. No Connect. Not internally connected. Ground connection. ISL45042A power supply input. Bypass to GND with 0.1F de-coupling capacitor. Internal Counter Up/Down Control and Internal EEPROM Programming Control Input. If CE is high, a mid-to-low transition increments the 7-bit counter, raising the DAC setting, increasing the OUT sink current, and lowering the divider voltage at OUT. A mid-to-high transition decrements the 7-bit counter, lowering the DAC setting, decreasing the OUT sink current, and increasing the divider voltage at OUT. Applying 4.9V and above with appropriately arranged timing will overwrite EEPROM with the contents in the 7-Bit counter. See EEPROM Programming section for details. Counter Enable Pin. Connect CE to VDD to enable adjustment of the output sink current. Float or connect CE to GND to prevent further adjustment or programming (note: the CE pin has an internal pull down resistor). Maximum Sink Current Adjustment Point. Connect a resistor from the SET pin to GND to set the maximum adjustable sink current of the OUT pin. The maximum adjustable sink current is equal to (AVDD/20) divided by RSET.
AVDD
N/C GND VDD CTL
CE
SET
Block Diagram
ISL45042A
CE 400k TO 500k UP DWN CTL DIGITAL INTERFACE WITH THRESHOLD SENSORS POR PRGM ANALOG DCP AND PWRUP UP/DOWN COUNTER WITH PRESET LATCHES CURRENT OUTPUT BLOCK SET AVDD
IBIAS
IOUT
READ
PRGM MEMORY
POR EEPROM OR PRGM NVL MEMORY
GND
VDD
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ISL45042A
Absolute Maximum Ratings
VDD to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+4V Input Voltages to GND SET, CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +4V AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +20V CTL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +17V Output Voltages to GND OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +20V ESD Rating Human Body Model for Device. . . . . . . . . . . . . . . . . . . . . . 2.75kV Human Body Model for CTL to GND (no EEPROM Content Disruption) . . . . . . . . . . . . . . . . . . . . . .8kV
Thermal Information
Thermal Resistance (Typical, Note 1)
JA (C/W)
8 Ld TDFN Package. . . . . . . . . . . . . . . . . . . . . . . . . 90 Moisture Sensitivity (see Technical Brief TB363) All Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 1 Maximum Junction Temperature (Plastic Package) . . . . . . +150C Maximum Storage Temperature Range . . . . . . . . . .-65C to +150C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Erase/Write Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10,000 Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . 10 years @ +85C
Operating Conditions
Temperature Range ISL45042AIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40C to +85C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTE: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379.
Electrical Specifications
Test Conditions: VDD = 3V, AVDD = 10V, OUT = 5V, RSET = 24.9k; Unless Otherwise Specified. Typicals are at TA = +25C SYMBOL TEST CONDITIONS TEMP (C) MIN (Note 8) TYP MAX (Note 8) UNITS
PARAMETER DC CHARACTERISTICS VDD Supply Range
VDD
For Programming For Operation
0 to 85 Full Full Full Full
3 2.6 4.5 0.7*VDD 0.2*VDD 20 20 0.64*VDD 4.9
10 1 -
3.6 3.6 50 20 20 20 0.8*VDD 0.3*VDD 200 200 10 10 10 0.4 15.75
V V A A V A V V s s s s s A A pF V V ms V
VDD Supply Current
IDD
CE = VDD (Note 6) CE = GND
AVDD Supply Range AVDD Supply Current CTL High Voltage CTL Low Voltage CTL High Rejected Pulse Width CTL Low Rejected Pulse Width CTL High Minimum Pulse Width CTL Low Minimum Pulse Width CTL Minimum Time Between Counts CTL Input Current
AVDD IAVDD CTLIH CTLIL CTLIHRPW CTLILRPW CTLIHMPW CTLILMPW CTLMTC ICTL CTL = GND CTL = VDD (Note 3) 2.6V < VDD < 3.6V 2.6V < VDD < 3.6V
Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full
CTL Input Capacitance CE Input Low Voltage CE Input High Voltage CE Minimum Start-Up Time CTL EEPROM Program Voltage
CTLCAP CEIL CEIH CEST CTLPROM
(Note 5) 2.6V < VDD < 3.6V 2.6V < VDD < 3.6V (Note 5) 2.6V < VDD < 3.6V, (Note 2)
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FN6158.3 August 29, 2007
ISL45042A
Electrical Specifications
Test Conditions: VDD = 3V, AVDD = 10V, OUT = 5V, RSET = 24.9k; Unless Otherwise Specified. Typicals are at TA = +25C (Continued) SYMBOL CTLPT PT SETVR SETDN SETZSE SETFSE ISET SETER Through RSET (Note 7) To GND, AVDD = 20V To GND, AVDD = 4.5V AVDD to SET Voltage Attenuation OUT Settling Time OUT Voltage Range OUT Voltage Drift NOTES: 2. CTL signal only needs to be greater than 4.9V to program EEPROM. 3. Tested at AVDD = 20V. 4. The Counter value is set to mid-scale 4 LSB's in the Production. 5. Simulated and Determined via Design and NOT Directly Tested. 6. Simulated Maximum Current Draw when Programming EEPROM is 23mA; should be considered when designing Power Supply. 7. A Typical Current of 20A is Calculated using the AVDD = 10V and RSET = 24.9k. Reference "RSET Resistor" on page 6. 8. Parts are 100% tested at +25C. Over-temperature limits established by characterization and are not production tested. AVDD to SET OUTST VOUT OUTVD (Note 5) to 0.5 LSB Error Band (Note 5) (Note 4) Monotonic Over-Temperature >4.9V TEST CONDITIONS TEMP (C) Full Full Full Full Full Full Full Full Full Full Full Full 25 to 55 7 10 2.25 VSET + 0.5V 7 20 1:20 20 <10 MIN (Note 8) 200 TYP MAX (Note 8) UNITS 100 7 1 2 8 200 45 13 s ms Bits LSB LSB LSB A k k V/V s V mV
PARAMETER CTL EEPROM Programming Signal Time Programming Time SET Voltage Resolution SET Differential Nonlinearity SET Zero-Scale Error SET Full-Scale Error SET Current SET External Resistance
Application Information
AVDD ISL45042A CTL CE SET RSET VCOM + GREEN BLUE RED OUT R2 ISINK AVDD R1
The application circuit to adjust the VCOM voltage in an LCD panel is shown in Figure 1. The ISL45042A has a 128-step sink current resolution. The output is connected to an external voltage divider, that results in decreasing the output VCOM voltage as you increase the ISL45042A sink current.
CTL Pin
The adjustment of the output VCOM voltage and the programming of the non-volatile memory are provided through a single pin called CTL when the CE pin is high. The output VCOM voltage is increased with a mid (VDD/2) to high transition (0.8*VDD) on the CTL pin. The output VCOM voltage is decreased with a mid (VDD/2) to low transition (0.3*VDD) on the CTL pin (Reference Figure 7). Once the minimum or maximum value is reached on the 128 steps, the device will not overflow or underflow beyond that minimum or maximum value. Programming of the non-volatile memory occurs when the CTL pin exceeds 4.9V. The CTL signal needs to remain above 4.9V for more than 200s. The level and timing needed to program the non-volatile memory is given in
COLUMN DRIVER
SINGLE PIXEL IN LCD PANEL
FIGURE 1. VCOM ADJUSTMENT IN AN LCD PANEL
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ISL45042A
Figure 2. It then takes a maximum of 100ms for the programming to be completed inside the device.
CTL VOLTAGE >200s
CE Pin
To adjust the output voltage, the CE pin must be pulled high (VDD). The CE pin has an internal pull-down resistor to prevent unwanted reprogramming of the EEPROM. The impedance of this resistor is 400k to 500k (RINTERNAL Figure 6). The CE pin has a Schmitt trigger on the input to prevent false triggering during slow transitions of the CE pin. Transitions of the CE pin are recommended to be less than 10s.
4.9V
CTLPT
TIME
FIGURE 2. EEPROM PROGRAMMING
Replacing Existing Mechanical Potentiometer Circuits
Figure 4 shows the common adjustment mechanical circuits and equivalent replacement with the ISL45042A.
When the part is programmed, the counter setting is loaded into the non-volatile memory. This value will be loaded from the nonvolatile memory during initial power-up or when the CE pin is pulled low. Once the programming is completed, it is recommended that the user float the CLT pin. The CTL pin is internally tied to a resistor network connected to ground. If left floating, the voltage at the CTL pin will equal VDD/2. Under these conditions, no additional pulses will be seen by the Up/Down counter via the CTL pin. To prevent further programming, ground the CE pin. CTL should have a noise filter to reduce bouncing or noise on the input that could cause unwanted counting when the CE pin is high. The board should have an additional ESD protection circuit, with a series 1k resistor and a shunt 0.01F capacitor connected on the CTL pin. (See Figure 3) To avoid unintentional adjustment, the ISL45042A guarantees to reject CTL pulses shorter than 20s. During Initial Power-up (only), to avoid the possibility of a false pulse (since the internal comparators come up in an unknown state), the very first CTL pulse is ignored. See Figure 7 for the timing information.
Expected Output Voltage
The ISL45042A provides an output sink current, which lowers the voltage on the external voltage divider (VCOM output voltage). Equation 1 and Equation 2 can be used to calculate the output current (IOUT) and output voltage (VOUT) values.
AV DD Setting I OUT = -------------------- x -------------------------20 ( R SET ) 128 R1 R2 Setting V OUT = -------------------- AV DD 1 - -------------------- x -------------------------- R 1 + R 2 20 ( R SET ) 128 NOTE: Where setting is an integer between 1 and 128. (EQ. 1)
(EQ. 2)
1k
ISL45042A CTL
0.01F
FIGURE 3. EXTERNAL ESD PROTECTION ON CTL PIN
AVDD Ra VCOM AVDD AVDD Rb + ISL45042A OUT R2 R1 = R a R2 = R b + R c RSET = (Ra(Rb + Rc)) / 20Rb RSET R1 +
VCOM
SET Rc
FIGURE 4. EXAMPLE OF THE REPLACEMENT FOR THE MECHANICAL POTENTIOMETER CIRCUIT USING THE ISL45042A
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FN6158.3 August 29, 2007
ISL45042A
Table 1 gives the calculated value of VOUT for resistors values of: RSET = 24.9k, R1 = 200k, R2 = 243k, and AVDD = 10V.
TABLE 1. CALCULATED VCOM OUTPUT VOLTAGES SETTING VALUE 1 10 20 30 40 50 60 70 80 90 100 110 128 VOUT 5.468 5.313 5.141 4.969 4.797 4.625 4.453 4.281 4.109 3.936 3.764 3.592 3.282
Verifying the Programmed Value
The following sequence can be used to verify the programmed value without having to sequence the VDD supply. To verify the programmed value, follow the following steps. The ISL45042A will read memory contents and be set to that value when the CE pin is grounded. 1. Power up the ISL45042A. 2. CE pin = VDD. 3. Change counter value with CTL pin to desired value. 4. CTL = more than 4.9V and 200ms. Counter value programmed. 5. Change the counter value with CTL pin to a different value. 6. CE pin = Ground. 7. Check that the output value is the one programmed in Step 4.
Generating VDD and CE supply from a Larger Voltage Source
The CE pin has an internal pull-down resistor (RINTERNAL Figure 6). The impedance of this resistor is 400k to 500k. If your design is using a resistor divider network to generate the 3.3V supply (for both VDD and CE to enable programming) from a larger voltage source, the 400k (worst case) resistor needs to be taken into account as a parallel resistance when the CE pin is connected to this source. Another design concern is to be able to provide enough supply current during programming. The ISL45042A draws about 2mA during this process. Recommended resistor values are shown in Figure 6. This design will result in an additional 0.83mA quiescent current flowing through resistors RA and RB.
VCC = 5V RA 2k CE VCE RB 4k RINTERNAL = 400k to 500k CE LOGIC SCHMITT TRIGGER ISL45042A
RSET Resistor
The external RSET resistor sets the full-scale sink current that determines the lowest voltage of the external voltage divider R1 and R2 (Figure 1). The voltage difference between the VOUT pin and ISET pin (Figure 5) has to be greater than 1.75V. This will keep the output MOS transistor in the saturation region. Expected current settings and 7-Bit accuracy occurs when the output MOS transistor is operating in the saturation region. Figure 5 shows the internal connection for the output MOS transistor. The value of the AVDD supply sets the voltage at the source of the output transistor. This voltage is equal to (Setting/128) x (AVDD/20). The ISET current is therefore equal to (Setting/128) x (AVDD/20 x RSET). The value of the Drain voltage is found using Equation 2. The values of R1 and R2 (Equation 2) should be determined (setting equal to 128) so the minimum value of VOUT is greater than 1.75V + AVDD/20.
SETTING AV DD ----------------------------x ----------------128 20 AVDD VOUT PIN AVDD = 15V R1 R2
VSAT 0.5V RSET
ISET PIN
FIGURE 6. APPLICATION GENERATING VDD AND VCE VOLTAGES
FIGURE 5. OUTPUT CONNECTION CIRCUIT EXAMPLE
Power Supply Sequence
The recommendation for power supply sequence would be to power down the part first (VDD, AVDD), after 100ms if programming has occurred, and then power down the control power supplies (CTL, CE).
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ISL45042A
ISL45042A Truth Table
The ISL45042A truth table is shown in Table 2. For proper operation the CE should be disabled (pulled low) before powering the device down to assure that the glitches and transients will not cause unwanted EEPROM overwriting.
INPUT CTL Mid to Hi Mid to Lo X >4.9V
.
TABLE 2. TRUTH TABLE OUTPUT VDD VDD VDD VDD VDD OUT Increment Decrement ICC Normal Normal MEMORY X X Read Program
CE Hi Hi Lo Hi
No Change Increased No Change Increased
CEST
CTLMTC
CTLIHRPW
CTL HIGH CTL VDD/2 CTL LOW CTLIHMPW CTLILMPW CTLILRPW
CE START PROGRAMMING
STOP PROGRAMMING START PROGRAMMING
COUNTER OUTPUT
UNDEF.
78
79
7A
7B
7A
NOTE: AFTER POWER IS 1ST APPLIED, THE VERY 1ST CTL PULSE IS IGNORED
IGNORES 1ST PULSE AFTER PROGRAMMING
VCOM
THE TIMING DIAGRAM ABOVE SHOWS POST POWER-UP TIMING.
FIGURE 7. ISL45042A TIMING DIAGRAM
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FN6158.3 August 29, 2007
ISL45042A Thin Dual Flat No-Lead Plastic Package (TDFN)
2X 0.15 C A A D 2X 0.15 C B
L8.3x3A
8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS SYMBOL A A1 MIN 0.70 NOMINAL 0.75 0.02 0.20 REF 0.25 0.30 3.00 BSC 2.20 2.30 3.00 BSC 1.40 1.50 0.65 BSC 0.25 0.20 0.30 8 4 0.40 1.60 2.40 0.35 MAX 0.80 0.05 NOTES 5, 8 7, 8, 9 7, 8, 9 8 2 3 Rev. 3 11/04 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals.
E 6 INDEX AREA TOP VIEW B
A3 b D D2 E
// 0.10 C 0.08 C
E2 e k L N Nd
A C SEATING PLANE
SIDE VIEW
A3
D2 (DATUM B) 1 2 D2/2
7
8
6 INDEX AREA (DATUM A)
NX k E2 E2/2
3. Nd refers to the number of terminals on D. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance.
NX L N 8 N-1 e 5 (Nd-1)Xe REF. BOTTOM VIEW C L NX (b) 5 SECTION "C-C" TERMINAL TIP FOR EVEN TERMINAL/SIDE e (A1) L1 10 L 0.10 M C A B NX b
8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Compliant to JEDEC MO-WEEC-2 except for the "L" min dimension.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 8
FN6158.3 August 29, 2007

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